Five-Stage, Power Efficient, Dual Rail, 100MHz, 10dB Programmable Gain Amplifier with Down-Stepping Functions in 28nm CMOS

With the continuous advancement of standards in telecommunication systems, requirements for analog circuitry become ever more demanding. The newer standards not only utilize better modulation schemes, demanding less noise with higher linearity, but also require increased bandwidth from analog circuitry. Together with performance, one of the most important key parameters is high efficiency. This paper describes a highly efficient, fully differential, five-stage, double feed-forward compensated, down stepping Programmable Gain Amplifier capable of providing DC gain from −12dB up to 10dB with 1dB steps for signal bandwidths of up to 100MHz. It consumes a total of 2.5mW-4mW of power from a split 1.8V/0.9V supply, while delivering a 1.2Vpp into a 1kΩ on-chip load. The PGA can support a maximum differential input swing of up to 5Vpp. The split architecture enables to run the first two gain stages of the amplifier from a 1.8V power rail and the latter three stages from a 0.9V power rail.