Study of integration issues in shallow trench isolation for deep submicron CMOS technologies

This paper presents a study of the issues in integrating the pattern, fill, planarization and surface cleanup processes to design a shallow trench isolation (STI) flow suitable for 0.25 micrometers CMOS technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data is presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.