Robust technique for on-chip DC current measurements

A robust and highly scalable technique for measuring DC currents is described. The circuit consists largely of digital electronics except for a comparator and a passive RC filter. This simple structure is able to force a voltage at a circuit node while measuring the current that flows into it. The technique has been successfully demonstrated using a prototype constructed using a 0.35mm CMOS chip. The demand for highly integrated mixed-signal ICs has increased rapidly in recent years. This is mostly driven by the communications industry. However, as the level of integration increases, more and more analogue components are becoming buried deep inside the digital circuitry without external I/O access. Consequently, initial device character- isation and production testing of these components has become more challenging. An area of IC testing that is being affected by this high level of integration are the DC parametric tests. These tests are conducted to characterise a wide variety of mixed-signal circuits such as analogue-to-digital converters (ADCs), PLLs and bias networks. Also, these tests are needed in digital test applications such as pad current leakage and IDDQ tests. One type of DC parametric tests that is of focus involves forcing a voltage at a circuit node while measuring the current that flows into it. The traditional method for on- chip current measurements is by using a transimpedance amplifier (1, 2), an integrating network (3, 4) or a shunt resistance (5). However, all of these circuits involve the use of elaborate ADCs with trimmed components, which makes them more expensive and relatively nonscalable for on-chip implementation. This paper presents a novel technique for force-voltage current measurements. It makes use of simple ADCs and programmable voltage references (DACs) to capture the DC transfer characteristic of an internal load at different current levels. Once known, the transfer characteristic of the internal load can be used indirectly to determine the value of an unknown current level connected to the test circuit. The proposed method requires mostly digital logic with the exception of a comparator and several passive RC components. As a result, the circuit architecture will be able to take advantage of the down-scaling of digital integrated circuit technology and not be affected by the reduction in power supply voltages. Also, the system is programmable,