Triple-Stacked Silicon-on-Insulator Integrated Circuits Using Au/SiO2 Hybrid Bonding

This study demonstrates a triple-stacking process of a silicon-on-insulator (SOI) wafer by repeating (1) the embedment of 5-μm-diameter gold (Au) electrode sites in a polished silicon oxide (SiO 2 ) surface, (2) Au/SiO 2 hybrid bonding with a thin silicon layer in between, and (3) subsequent lost-wafer processes. Inverters prepared on separate SOI wafers are vertically connected through Au electrodes. Feasibility tests are performed by developing triple-stacked ring oscillators (ROs) with 101 stages. The experimental results confirm a successful RO operation and indicate that the developed process is promising for three-dimensional integrated circuits using the multi-wafer stacking technique.