Opportunities and challenges in device scaling by the introduction of EUV lithography

EUV lithography is generally considered as the technology to take over from 193nm immersion lithography, but has been delayed due to a number of critical problems that remain to be solved. The purpose of this paper is to illustrate the improvements in process complexity, reduced design restrictions and reduced processing costs in case EUVL would be available for the 14nm logic node and beyond. We have shown that the readiness of EUVL is critical to keep scaling the logic devices following the pace of Moore's law, continuing the performance improvements of the devices at an acceptable processing cost and cycle time, still allowing sufficient freedom to the system designers in terms of design restrictions.