Dc and low frequency noise analysis of hot-carrier induced degradation of low complexity 0.13 μm CMOS bipolar transistors

The dc and the low frequency noise in Si bipolar junction transistors (BJTs) of a 0.13 μm CMOS technology are presented in this paper. In particular, the influence of a superficial base doping (SBD) layer is investigated in devices before and after hot-carrier stress induced degradation. A classical increase in the perimeter non-ideal (generation/recombination) base current is observed on stressed transistors. Prestress 1/f noise analysis shows that both surface and perimeter contribution are present. Their relative importance is dependent on presence or not of the SBD and of the geometry. After stress, a very significant increase in the 1/f noise level is measured. It is associated to the creation of a large number of traps at the emitter perimeter.