Fast parallel CRC & DBI calculation for high-speed memories: GDDR5 and DDR4

In this paper, a new XOR gate and architecture for parallel calculation of CRC and DBI are proposed. With this proposal, speed constraints in high-speed DRAMs such as GDDR5 and DDR4 SDRAM are relaxed. This helps minimize the latency increase and hence the effective bandwidth loss from CRC and DBI functions.