Effect of interface state trap density on the characteristics of n-type, enhancement-mode, implant-free In0.3Ga0.7As MOSFETs

The effect of interface state trap density, D"i"t, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In"0"."3Ga"0"."7As MOSFETs [1,2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary D"i"t distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0@mm gate length IF In"0"."3Ga"0"."7As MOSFETs [3]. The impact of interface states on a scaled 30nm gate length IF MOSFET is also reported.