Effects of Parasitic Capacitance, External Resistance, and Local Stress on the RF Performance of the Transistors Fabricated by Standard 65-nm CMOS Technologies

Effects of parasitic capacitance, external resistance, and local stress on the radio-frequency (RF) performance of the transistors fabricated by 65-nm CMOS technology have been investigated. The effect of parasitic capacitance, particularly C gb , becomes significant due to the reduced spacing between the gate and the substrate contact (SC) in proportion to scaling down. Current drivability (I dsat ) per unit width has been improved through introduction of mobility enhancement techniques. The influence of external resistance becomes more pronounced for large-dimensional RF transistors due to severe IR drop. Such improved current drivability and large external resistance is responsible for dc performance (g m ) degradation and, eventually, cutoff frequency (f T ) degradation. Local stress effects associated with silicon nitride capping layer and STI stress have been investigated. f T is largely affected by local stress change, i.e., g m degradation at minimal gate poly (GP) pitch and gate-to-active spacing, f T is dominated by increased parasitic capacitance (C gb ) with increasing GP pitch and gate-to-active spacing. Above 10% improvement in f T has been observed through layout optimization for C gb reduction by increasing the transistor active-to-SC spacing.