FlexFET: a low-cost planar, self-aligned independent-double-gate MOSFET with flexible, dynamic threshold control

A variety of double-gate (DG) MOSFET transistor structures are being developed to permit scaling to the sub-50nm regime. However, flexible dynamic threshold voltage control is urgently needed for ultra-low-power digital circuits, novel analog/RF circuits, and dynamically reconfigurable & self-repairing circuits (Yang et al., 1997). Independently-double-gated (IDG) FinFETs have recently been reported to have highly-controllable V/sub t/ without the use of multiple masks & implants (Liu et al., 2003; Liu et al., 2004; Fried et al., 2003). However, a lithographically-defined fin width of >10nm is required to achieve /spl Delta/V/sub t/=0.8V/V. The few recently reported planar IDG MOSFETs have oversized, nonself-aligned bottom gates and/or require epitaxial channel growth (Tanaka et al., 1991; Harrison et al., 2003; Guarini et al., 2001). We introduce FlexFET, a low-cost planar IDG MOSFET, with a damascene metal topgate and an implanted JFET bottomgate that are self-aligned in a gate trench. This new device is highly scalable, due to its sub-lithographic undoped channel, nonimplanted ultrashallow SDEs, nonepi raised SD's, and "gate-last" flow. Most damascene gate processes use a dummy gate and implanted SDE junctions. FlexFET utilizes a spacer-lined gate trench (Chen et al., 2000; Matsuo et al., 2002) that is etched through implanted SD regions to self-align its implanted JFET bottomgate with its TiN topgate. The top and bottomgates are connected at opposite edges of the device by a damascene local interconnect (LI) that is embedded in the STI regions between devices, resulting in high layout density. Since the top gate is CMPed, and the SDEs are not implanted, there is no damage to the channel edges. Effectively "raised" SDs are achieved without using selective epi. Sidewall spacers narrow the gate trench opening, resulting in >180nm channel lengths, even with low-cost relaxed 350nm lithography.