23.8 A 41μW 16MS/s 99.2dB-SFDR Capacitively Degenerated Dynamic Amplifier with Nonlinear-Slope-Factor Compensation

The amplifiers used to improve the noise performance in analog front-ends and ADCs must have sufficiently low noise and high linearity to achieve overall system performance targets. Achieving the target noise level requires a certain amount of power, but nonlinearity can be improved by analog or digital techniques. Residue amplifiers used in pipelined ADCs have been improved to dissipate low power, preserving their linearity. Traditionally, closed-loop amplifiers with high open loop-gain are used for the residue amplifiers [1], but they require static current, thus degrading power efficiency. To improve the power efficiency of the residue amplifier, dynamic amplifiers have been investigated [2], [4], which allow using only the required bandwidth, thus minimizing the power consumption for a given noise requirement. However, a dynamic amplifier requires digital calibration to compensate for the nonlinearity, increasing the design complexity and limiting the robustness to PVT variations [2], [3].