A Novel Metal Scheme and Bump Array Design Configuration to Enhance Advanced Si Packages CPI Reliability Performance by Using Finite Element Modeling Technique

Flip chip packages with Cu bump have been introduced in recent years to address the needs of advanced packaging for reducing bump pitch and increasing I/O density, which can also enhance performance and offer a cost effective solution with smaller form factor. Moreover, Cu interconnect with extra low-k (ELK) dielectric material was also applied to reduce power consumption and further enhance device performance, especially for advanced silicon nodes. Due to the nature of ELK dielectric material characteristics, it is more sensitive while a flip chip package using Cu bump with ELK dielectric, and subjected to thermal loading conditions. Thermal stresses are induced in Si/package due to the coefficients of thermal expansion (CTE) mismatch among different packaging materials under thermal loading. ELK dielectric delamination/cracking during chip-package-interaction (CPI) related reliability tests, is a primary concern in the advanced Si packaging development and quick thermal cycling (QTC) test has been widely used to assess the CPI reliability performance for newly developed packages. From the past experience, "white bump" issue, which is related to ELK delamination, is mainly caused by excessive ELK stresses, and appeared within 1~3 bump pitches range from die edge or corner due to CTE mismatch between die (~2.8 ppm/oC) and organic substrate (~17 ppm/oC). The previously proposed solutions include die/substrate co-design, substrate selection, underfill/TIM/adhesive materials selection, and heat spreader design. However, more and more QTC test results indicate that the configuration of top metal layout and bump pattern can also affect the ELK reliability significantly. This work investigated advanced Si package ELK reliability performance from die attach (using conventional reflow process) to subsequent QTC tests. A three-dimensional (3-D) nonlinear finite element method is applied, and a two-level of specified boundary condition (SBC) of global-local technique are adopted to achieve more accurate resolution. Meanwhile, modeling results were calibrated with experimental package warpage measurements. The modeling predictions were also compared with QTC test data and obtained good agreements. Based on collected modeling and test data, it was revealed that higher density and more uniform pattern in both top metal and bump layouts could relieve ELK thermal stresses significantly. The proposed methodology in this paper had been validated and design guideline will be proposed upon the findings of this study, which product / package designers can benefit from the superior device / package performance provided from the integration of Cu interconnect and ELK dielectric, meanwhile, alleviate potential CPI related risks while using advanced Si packaging.