A Current-Gain Scheme for High Density and Low Voltage FeRAM

The proposed current-gain scheme provides a key technical solution for a high density, low cost and high performance ferroelectric random access memory. The proposed sensing scheme shows maximum sensing-signal window because of divided sub-bitline (SBL) structure. The unit cell array section is composed of the cell array of 64 rows and 128 columns with SBL, SBL switch (SBSW) devices and current-gain transistor (CGT) device. The global main bitline (MBL) is biased by MBL sensing load (MSL) device and connected to common MBL bus (CMB) through block selection switch (BSS) device. The device sizes of CGT and MSL devices are key factors for determining the transfer characteristics of SBL and MBL. The 128 sense amplifiers in peripheral circuit region are shared to all cell array blocks through CMB with 128 MBL columns of each cell array block. The address access time of the 16 Mb chip is evaluated to less than 70 ns at 3 V.