A Two Conversions/Sample Differential Slope Multiple Sampling ADC With Accelerated Counter Architecture

Introduction In recent years, the noise performance of CMOS image sensors has improved significantly with the implementation of a multiple sampling architecture [1-3]. In the multiple sampling architecture, the thermal noise of the pixel source follower can be reduced by a factor equal to the square root of the sampling number. The multiple sampling architectures usually employ single slope (SS) ADCs, which have a simple circuit topology, good linearity and noise performance. A low noise level of around 1 electron has been achieved [2,3]. However, one disadvantage of SS-ADCs for multiple sampling is the conversion time which increases exponentially with the number of bits. The noise reduction effect of the multiple sampling was limited by the noise in the frequency domain, i.e., 1/f noise from the pixel source follower, as the sampling time increases [2]. In the meantime, the noise level is still too high to allow a standard CMOS image sensor to perform at an ultra-low light level. To reduce the frequency domain noise, a decrease of the conversion time of the multiple sampling ADC is required. A higher clock frequency of the SS-ADC increases the operation speed, but it requires high power consumption with high thermal noise which also degrades the signal quality. Two-step A/D conversion architecture of SS-ADC has also been proposed [4,5], but they degrade the linearity and hence the image quality. This paper introduces a differential slope (DS) ADC with a multiple sampling architecture for low noise CMOS image sensors. The DS-ADC achieves half the conversion time of the multiple sampling compared to the SS-ADC at the same clock frequency while preserving the key benefit of the SS-ADC. Employing counter acceleration architecture in the DS-ADC also halves the maximum power consumption of the digital counter.