A planar transistor for the 32-nm node and beyond with an ultra-shallow junction fabricated using in-situ doped selective Si epitaxy

Shallower junctions must be formed to make transistors work for the 32-nm node. Many kinds of technologies, such as co-implantation, Laser Spike Annealing (LSA), and flash lamp annealing, have been energetically studied to form ultra-shallow junctions. We focused on in-situ doped selective Si epitaxy, with which the short channel effect and the parasitic resistance can be made compatible. Using this epitaxy, ultra-shallow junctions (with effective junction depths (Xj, eff) under 9 nm@5E18) were formed, and 20-nm or shorter PMOS gate transistors were fabricated using the epitaxy.