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Y. Tagawa

Sony Broadcast & Professional Research Laboratories

18

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95

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Planar Metal–Oxide–Semiconductor Field-Effect Transistors with Raised Source and Drain Extensions Fabricated by In situ Boron-Doped Selective Silicon Epitaxy

2010 Japanese Journal of Applied Physics
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Novel Damascene Gate Metal–Oxide–Semiconductor Field-Effect Transistors Fabricated by In situ Arsenic- and Boron-Doped Epitaxy

2010 Japanese Journal of Applied Physics
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High Performance and High Reliability Dual Metal CMOS Gate Stacks Using Novel High-k Bi-layer Control Technique

2007 VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
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Tinv Scaling and Jg Reducing for nMOSFET with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone Water Treatment Process

2007 The Japan Society of Applied Physics
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Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

2007 IEDM | International Electron Devices Meeting
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PMOSFET Vth Modulation Technique using Fluorine Treatment through ALD-TiN Suitable for CMOS Devices

2007 The Japan Society of Applied Physics
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Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

2007 VLSIT | Symposium on VLSI Technology
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A planar transistor for the 32-nm node and beyond with an ultra-shallow junction fabricated using in-situ doped selective Si epitaxy

2006 ESSDERC | European Solid-State Device Research Conference
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High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

2006 VLSIT | Symposium on VLSI Technology
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A Promising Planar Transistor with in-situ Doped Selective Si Epitaxy Technology (GORES MOSFET) for 32nm node and beyond

2006 VLSI-TSA | International Symposium on VLSI Technology, Systems, and Applications
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