A path toward high voltage devices : 3.3 kV 4H-SiC JBS and JFET

In the context of higher voltage reaching, this study presents the methodological design of a 3.3kV 4H-SiC JFET. Different criteria have been studied to determine optimized values for the critical parameters. By taking account of the technological process limitations, we were then able to fabricate the device and reach our aim. The device is classically formed of a drain electrode on the rear face of the wafer, which funnels the current to a source electrode via a channel, controlled by a gate electrode.