A 1856 I/O cell CMOS SOG with half-ns clock skew and a 6 ns RAM

A 177 K CMOS sea-gates has been developed by applying a 0.8- mu m triple-metal-layer process technology. Its speed reaches 200 ps, and 120 K usable gates can be provided. A high-speed RAM (6 ns typical access time) of high-density type (64 kbit maximum) can be implemented on it. It has 1856 I/O cells which offer much flexibility in the construction of I/O buffers. >