A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET

This paper presents a flexible 0.5–16.3Gb/s serial transceiver - fabricated in 16nm FinFET CMOS - and consuming 219mW/channel at 16.3Gb/s. The transceiver is fully adaptive to cover the FPGA requirement to interface to a multitude of combinations of data-rates and standards, such as 10G KR, PCIe Gen3/4, across a range of channel loss profiles. High performance techniques employed include a fully adaptive CTLE, AGC, an 11-tap DFE, wide-band LC PLLs and a low-latency CDR+PI for high-tracking-bandwidth clock and data recovery. Low power techniques such as half-rate clocking, DFE speculation, active inductors and data-rate-binned design are employed to meet stringent power budgets. At 16.3Gb/s, the receiver has a jitter tolerance of 0.3UI at 100MHz and the transceiver achieves BER −15 with up to 28dB loss at Nyquist.