Silicon defects characterization for low temperature ion implantation and spike anneal processes

In the last years a lot of effort has been directed in order to reduce ion implantation damage, which can be detrimental for silicon device performances. Implantation's dose rate and temperature were found to be two important factors to modulate residual damage left in silicon after anneal. In this work high dose rate, low temperature, high dose arsenic and boron implantations are compared to the corresponding low dose rate, room temperature processes in terms of silicon lattice defectiveness and dopant distribution, before and after anneal is performed. The considered implant processes are the one typically used to form a source/drain region in a CMOS process flow in the submicron technology node. A spike anneal process was applied to activate the dopant. Low temperature, high dose rate implantations have found to be effective in reducing silicon extended defects with a negligible effect on the profile of the activated dopant. Experimental set up, results and possible explanation will be reported and discussed in the paper.