Managing SRAM reliability from bitcell to library level

Static Random Access Memories (SRAMs) are present nowadays in all CMOS products in large quantities. Besides, they are often very challenging both on process side (due to small dimensions) and on design side (due to performance request). As a consequence, managing their reliability is of prime importance, though it is quite complex due to their overall complexity. This paper demonstrates a full reliability-based design flow for SRAM libraries including both Front-End degradation modes (NBTI, PBTI and HCI) as well as Back-End degradation modes (Electromigration). Large experimental datasets on various technologies and SRAM bitcells have been used all along the paper to show clear Silicon-CAD correlation evidences, demonstrating the efficiency and accuracy of the developed flow.