Mapping Conductance and Carrier Distributions in Confined Three-Dimensional Transistor Structures

Probing the distribution of charge carriers in semiconductor device structures is of crucial importance to better understand semiconductor fabrication processes and how they affect the incorporation, diffusion and activation of dopants and hence the final device performance. Scanning spreading resistance microscopy (SSRM) has emerged as the most valuable technique for 2D and 3D carrier mapping in semiconductor device structures due to its excellent spatial resolution, sensitivity and ease of quantification. The present chapter first introduces the principles of the technique, thereby discussing the underlying physical mechanisms such as the nanometer-size probe-semiconductor contact. Faced with the stringent requirements imposed by advanced 3D device architectures, novel approaches and concepts such as 3D carrier profiling and fast Fourier transform-SSRM (FFT-SSRM) have been developed in the recent years. These methods aid in extending conventional SSRM toward quantitative carrier profiling in aggressively scaled 3D device structures which is illustrated on the example of selected relevant applications such as FinFETs and nanowire-based transistors.