Rapid full-chip curvilinear OPC for advanced logic and memory

The patterning requirements of next generation lithographic processes and the desire to keep manufacturing costs down have pushed the lithographers to explore the advantages of the curvilinear masks. Multiple studies backed by the experimental results have demonstrated the lithographic advantage of the curvilinear (CL) photomasks over the rectilinear (RL) approximations by showing improved MEEF, depth of focus (DoF) and common DoF (CDoF) for variety of patterns on the same mask, ILS and, as a result, process window (PW) of the CL masks over its close RL siblings [1,2]. Manufacturability of the CL masks has been limited due to the architecture of the Variable Shaped Beam (VSB) writers, which made it prohibitive from both mask data preparation (MDP) and mask writing perspective. The availability of Multi Beam Mask Writers (MBMW) has removed these roadblocks and brought introduction of the curvilinear masks much closer to reality. The development of novel approaches for MDP and Mask Proximity Correction (MPC) as it is demonstrated by Bork et al in [3] brought further advances in availability of the CL masks for high volume manufacturing (HVM). Traditionally the Inverse Lithography Technology (ILT) has offered the most potential to achieve significant lithographic advantage over RL masks but has suffered from very long data preparation runtimes which presented an additional hurdle for broad deployment in manufacturing. While various speed up options such as machine learning-based acceleration, and GPU processing [4,5] are being explored, the full chip ILT run time still represents significant challenge in the HVM world. This paper will concentrate on two OPC approaches that allow CL mask generation without run time penalties associated with full chip ILT processing. The first is based on a hybrid methodology that allows for generation of the CL mask shapes by using fast ILT-based algorithms for SRAF generation while the main features are controlled to allow for full chip processing within the reasonable time. The second approach is more appropriate for the memory applications where patterns are highly repetitive. Due to high level of repetition, it is acceptable to use full ILT correction carried over a small area of the chip and to utilize pattern matching (PM) methodologies to propagate both SRAFs and OPC-corrected features from unique to non-unique pattern placements. Such a methodology allows for the full ILT advantages in the highly critical memory array areas.