A pipeline time-to-digital converter with a programmable time amplifier

This paper presents a pipeline time-to-digital converter (TDC) using a programmable time amplifier (TA). The TA adds time intervals that contain quantization errors in different stages of the first conversion step to achieve time amplification. Therefore, the TA has advantages of programmability, good linearity and wide input range. The TDC is designed in a 65nm CMOS technology. A time resolution up to 5ps at 230MHz is achieved. The total power consumption is 3mW under a 1V supply.