Conducted emissions in a 40 nm CMOS test chip: The role of the ESD protections

This paper briefly recalls the design of a silicon test chip specially conceived to study the noise propagation trough the silicon substrate and the ESD protection. The noise source is a logic block designed to emulate the clock tree of a microcontroller. The experimental results obtained on two versions of the test chip are reported and discussed. The two test chips have the same schematic, but they differ in ESD protections: in the first one the protections were completely removed, while the second test chip has ESD protections both on VDD and VSS. This allows to study the effect of the protection structures on the noise propagation through the different power domains and the substrate. Dedicated probe points have been introduced in the layout around the perimeter of the die. The measurements of the conducted emissions at the substrate probes and on the power supply pins have been performed according to the IEC61967-4, 150Ω method.