Negative Bias Temperature Instability of SiC MOSFET

MOSFETs and MOS capacitors (MOSCAPs) have been fabricated on Si-face of 4H-SiC to investigate the negative bias temperature instability (NBTI) characteristics of SiC MOSFETs. The shifts of threshold voltage of MOSFETs ranged from -216mV to -1257mV after stressed by 1000sec of -1V to -15V gate bias, correspondingly. The negative shift of the threshold voltage indicated that there were positive charges piled up at or near the oxide/SiC interface. In the mean time, the flat-band voltage shifts of SiC MOSCAPs using the same oxide after stressed by -15V bias for 28800 sec at 175°C were negligible, due to insufficient supply of holes, thus suggesting that the NBTI observed in this study was primarily participated by hole trapping, instead of electron emission. The time evolution of DVth induced by negative bias stress was found to saturate quickly, also suggesting that positive charges were primarily coming from trapping of pre-existing near-interface oxide traps, instead of generation of interface traps. The DVth induced by negative bias stress was lower at higher temperature which might be attributed to faster recovery of hole trapping at elevated temperature.