Superior nMOSFET scalability using Fluorineine co-implantation and spike annealing

The paper reports the simultaneous improvement of both on- and off-properties for nMOSFETs by means of fluorineine co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with fluorineine co-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted and C co-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (R EXT ) vs. effective channel length (Leff) trade-off are examined