Understanding and improving SILC behavior under TDDB stress in full gate-last high-k/metal gate nMOSFETs

Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress. However, the interfacial layer quality can be a critical SILC issue in FGL devices.