A novel approach for full-chip SRAF printability check

With the critical dimension of IC design decreases dramatically, to meet the yield target of the manufacture process, resolution enhancement technologies become extremely important nowadays. For 90nm technology node and below, sub rule assistant feature (SRAF) are usually employed to enhance the robustness of the micro lithography process. SRAF is really a powerful methodology to push the process limit for given equipment conditions. However, there is also a drawback of the SRAF. It is very hard to predict the printability of the SRAFs, especially when SRAF is applied on full chips. This work is trying to demonstrate a new approach to check the printability of the SRAF on full-chip level. First, we try to capture the lithography process information through real empirical wafer data. Then we try to determine the margin of the conditions for which SRAFs can be printed out on the wafer. Based on all the information, we can then apply full chip optical rule check (ORC) to check the printability of SRAF. By this approach, the printout risk of the SRAF can be reduced effectively with acceptable time consuming.