Formation of a submicron GaAs MESFET gate using a four-layer dielectric dummy gate

In the present study, a technology for the formation of a submicron GaAs MESFET gate of 0.5–0.1 μm in length and above 0.5 μm in height using a four-layer dielectric dummy gate was developed. Techniques of chemical and plasma-chemical deposition from a gaseous phase, differing in etch rates in a buffer solution of hydrofluoric acid, were used to prepare silicon oxide films. Different constructions of a multilayer structure with varying sequences of layers and thicknesses were studied. The conditions of chemical and plasma-chemical etching of dielectrics allowing a dummy double-T-gate to be formed were determined. The employment of a sophisticatedly shaped dummy gate made it possible to obtain a gate electrode of a large cross section with a low length. The possibility in principle to fabricate a MESFET gate with a length of up to Lg = 0.1 μm using lithographic procedures with a minimal resolution of 1.0 μm was demonstrated.