A Top-Down Approach for Low Noise Amplifier Design using Verilog-A

A 2.4 GHz low noise amplifier (LNA) was designed in a 65nm CMOS process using a top-down design methodology. The gain, noise, linearity, and power consumption of the LNA were modeled using Verilog-A. The model provides an overview of the performance trade-offs along with the biasing and sizing parameters that satisfy a target specification. The designed LNA was measured to have a voltage gain of 18.56 dB, a noise figure of 0.94 dB, an IIP3 of -8.01 dBm, and a power consumption of 3.79 mW.