FPGA Implementation of the Single Thalamic Neuron Model

Thalamic neurons play an important role as a relay station for the transmission of sensorimotor signal to the cortex. In this study, a Hodgkin-Huxley (HH) type thalamic neuron model was designed and implemented on Field Programmable Gate Arrays (FPGA). In order to reduce hardware resources, the Finite State Machine (FSM) was proposed to control the data flow of Look-Up-Tables (LUTs) modeling nonlinear functions of the thalamic model. Besides, LUTs were controlled to seek different values in different clock periods. The simulation error between hardware and software implementation methods are analyzed. Compared to the original implementation that each nonlinear function is implemented with one LUT, the hardware implementation method proposed in this paper reduces memory resources by about 61 %, but increases the logical resources by 24%. It reduces the overall cost of resource, which lays the foundation for us to realize the large-scale neural network.