Development of plasma etching process for sub-50 nm TaN gate

Abstract TaN has been identified as a possible candidate to replace polysilicon for sub-50 nm gate CMOS transistors. However, TaN gate etching in CD (critical dimensions) range below 100 nm presents a great challenge and not much information is available in this area. Using thin layer of SiO 2 as a hard mask, TaN etching was evaluated in DPS (decoupled plasma source) etcher with four gas chemistries: Cl 2 , Cl 2 /BCl 3 /Ar, Cl 2 /BCl 3 , and Cl 2 /Ar. Due to lesser CD gain and higher selectivity to gate dielectrics, Cl 2 /Ar was chosen for further optimization by DOE. Based on the analysis of the effects of input parameters on the etch responses, we developed a two-step etch process with sub-50 nm minimal CD, profile close to vertical, and capability to stop on 5 nm HfAlO high-k dielectric. 60-nm gate transistors with TaN-HfAlO gate stack (equivalent oxide thickness of 2.5 nm) were fabricated with reasonably low gate leakage of 10 − 2 A/cm 2 at gate bias of 1 V and absence of polysilicon depletion effect.