Analysis of defect to yield correlation on memories: method, algorithms and limits

Memory circuits are excellent vehicles for yield enhancement of a process technology for VLSI products. A method was developed which consists of correlating the physical defects detected by in-line inspections with the electrical failures. In this method, two types of errors can affect results. A model is proposed in order to estimate and minimize the number of errors. The defect-yield correlation on memories indicates the priority problems responsible for yield loss. Nevertheless, the contribution of the killer defects detected by in-line inspections to yield loss has to be verified. New algorithms are proposed to provide this data that is often missing in yield management systems.