An iterative calculation method of the neuron model for hardware implementation

Artificial neural networks (ANN) have the potential of parallel processing by the integrated circuit technology. Recently, over one million gates are available by the latest field programmable gate array (FPGA). However, the sum-of-product circuit used for evaluating the inputs of a neuron model is complex and not effective for hardware implementation by FPGAs. In this paper, an improved calculation algorithm of the perceptron-type neuron model is proposed, which is based on the multidimensional binary search. Since the search does not need the sum-of-product circuit, the designed neuron circuit is small and fast and is suitable for hardware implementation.