A SONOS device with a separated charge trapping layer for improvement of charge injection

A charge trapping layer that is separated from the primary gate dielectric is implemented on a FinFET SONOS structure. By virtue of the reduced effective oxide thickness of the primary gate dielectric, a strong gate-to-channel coupling is obtained and thus short-channel effects in the proposed device are effectively suppressed. Moreover, a high program/erase speed and a large shift in the threshold voltage are achieved due to the improved charge injection by the reduced effective oxide thickness. The proposed structure has potential for use in high speed flash memory.