Byte alterable embedded EEPROM with B4-HE architecture achieving 10usec programming and 57F2 cell size

This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabricated using a 90 nm flash process, and single-pulse program and erasure cycling has been confirmed up to one million, with keeping programming time of 10 us and erase time of 1 ms. It is demonstrated that the excellent capability of more than 10 years data retention at 150 C. In addition, a fully designed 90 nm B4-EEPROM macro specification has been investigated, and the unit cell size can be designed 57F2, which is a half those of conventional EEPROM cell size of 80-100F2.