Passive slew rate enhancement technique for Switched-Capacitor Circuits

A passive charge compensation technique is proposed for switched capacitor circuits which increases the slew rate of its amplifiers. Higher linearity can be achieved by adding a small amount of circuitry with low power consumption. The proposed technique is implemented in a single-bit discrete time second-order delta sigma modulator in 65-nm CMOS technology, where simulation results show an improvement of 12 dB SNDR. Alternatively, the same performance can be achieved with almost half of the power consumption with charge compensation circuit activated.