Alternatives for rear-surface passivation in III–V on Si multi-junction solar cells

In the recent developments in the field of III–V on Si dual-junction solar cells, low attention has been paid to optimizing the device configuration to maximize its photovoltaic performance. The few practical implementations reported heretofore have been based on III–V solar cell processing techniques. Although the fabrication of conventional Si structures is a well-known technology, certain steps have been found to be incompatible with III–V semiconductors, primarily due to their high thermal load. Accordingly, in this work we discuss the applicability of different alternatives for the Si rear-surface passivation (Al-BSF, PERC- and HIT-like schemes) in III–V/Si dual-junction solar cell structures. Using numerical simulations, a comparison of the Si bottom cell performance in a GaAsP/Si dual-junction solar cell structure is presented for the mentioned alternatives.