Back-end soft and hard defect monitoring using a single test chip

Abstract The objective of this paper is to present a mixed test structure designed to characterize yield losses due to hard defect and back-end process variation (PV) at die and wafer level. A brief overview of the structure, designed using a ST-Microelectronics’ 130 nm technology, is given. This structure is based on a SRAM memory array for detecting hard defects. Moreover each memory cell can be configured in the Ring Oscillator (RO) mode for back-end PV characterization. The structure is tested in both modes (SRAM, RO) using a single test flow. The test data analysis method is presented and applied to experimental results to confirm the ability of the structure to monitor PV and defect density.