Modeling of BTI-aging V T stability for advanced planar and FinFET SRAM reliability

In this study, the comparison of time-zero V t and Bias-Temperature Instability (BTI) induced Vt shift on advanced planar (20nm System-on-Chip, 20SoC) and FinFET (16nm FinFET, 16FF) is investigated, which is modeled by Dispersive Skellam (DS) cumulative distribution framework. As a result of the much better time-zero Vt mismatch and less V T shift spread in FinFET devices, the SRAM static noise margin (SNM) shift distribution of 16FF is less than 20SoC planar technology node. We present a universal picture of time-zero Vt and BTI-aging V T shift management to correlate SRAM bit cell SNM shift, which offers a prospected approach for advanced planar and FinFET SRAM reliability optimization.