Multiplexing Firmware Prototypes for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

As part of the ATLAS experiment’s Phase-II Upgrade, improved trigger hardware and algorithms will be implemented onto a single-level architecture. The global trigger (GT) subsystem is a new firmware (FW)-focused project designed to meet stringent requirements from the high-luminosity runs of the large hadron collider (LHC). The global multiplexer (MUX) is the input aggregating stage of the GT; it performs three main tasks: 1) aggregating data from several sources, connected with more than 2300 input fibers, under different protocols; 2) time-multiplexing the incoming data, to sort the packets per bunch-crossing (BC) events, by compensating the relative skews across the various serial input channels; and 3) transmitting, in a round-robin fashion, the sorted BC data to the global event processor (GEP) array, which is the following stage of the GT subsystem and is composed of 48 nodes, each one processing a single BC event. Two MUX FW prototypes for the Global Feature EXtractor (gFEX, part of the liquid argon calorimeter trigger) inputs have been designed, implemented, and validated on a gFEX production board, for up to 72 input and output channels. A four-channel version has been completed with I/O interfaces and validated in a full-chain design, accepting 8b/10b encoded inputs at 11.2 Gb/s and transmitting at 25.78125 Gb/s under Xilinx Aurora 64b/66b protocol. The total latency has been benchmarked in all of its contributing subcomponents and proven to meet the requirements from the Technical Design Report for the Phase-II Upgrade of the trigger and data acquisition system.