Avalanche rugged 1200 V 80 m Ω SiC MOSFETs with state-of-the-art threshold voltage stability

1200 V 80 m Ω SiC MOSFETs were developed for 150 mm wafer mass production. Avalanche ruggedness was confirmed by measuring the failure distribution in unclamped Inductive switching (UIS) for five wafers. The high voltage blocking reliability was verified by running 1000hr high temperature reverse bias tests for totally 770 devices without failures. The process conditions were optimized for gate oxide integrity and to minimize threshold voltage (V TH ) drift both during positive and negative bias stress. Significant reductions of extrinsic defects in the gate oxide breakdown distributions were obtained using optimized process conditions for both product dies and NMOS capacitors. State-of-the-art V TH stability was verified by transient measurements of V TH drift during gate bias stress for packaged 80 m ΩSiC MOSFETs.