Design of Low-Power Multiplier Using UCSLA Technique

Multiplication is one of the major fundamental operations and key hardware blocks in any digital system. This paper presents the comparison of the VLSI design of uniform carry select adder (UCSLA)-based multiplier technique with the variable carry select adder (VCSLA)-based multiplier technique. The analysis is carried out on the different bit sized values of unsigned inputs, and output results show that the area, power, and delay are reduced in the UCSLA-based multiplier technique compared to VCSLA-based technique. The timing delay in 64-bit VCSLA-based multiplier technique is 95.25 ns for performing the multiplication, which is reduced by 11.11 % in the UCSLA-based multiplier technique. In the same manner, area is reduced by 39.42 % and power also reduced by 19.28 % in UCSLA-based multiplier technique. The simulation works of multipliers are carried out in Verilog-HDL (Modelsim). After the simulation, the results are obtained using cadence tool.