Reliability issues of silicon LSIs facing 100-nm technology node

Abstract Reliability issues regarding scaled silicon devices are reviewed from the viewpoint of the 100-nm technology node. Topics covered include hot carrier degradation, negative bias-temperature instability, boron penetration, interface properties of a high- k dielectric film, and stress-induced leakage current of a floating-gate-type non-volatile memory. Soft error by terrestrial neutrons is also discussed as an emerging reliability issue. In addition, copper-wiring reliability is extensively reviewed from the viewpoint of further miniaturization.