Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Abstract The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its improved electrostatics and short-channel effect control. FinFETs represent one of the architectures of interest within that family together with Ω-gates, Π-gates, gate-all-around… They can readily be manufactured starting from SOI or bulk substrates even though more efforts have been dedicated to the SOI option so far. We report in this work an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations. Both alternatives show better scalability (threshold voltage – V t vs. L ) than PLANAR CMOS and exhibit similar intrinsic device performance ( I off vs. I on ). Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced threshold voltage mismatch. Using an optimized integration to minimize parasitic capacitances and resistances we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both SOI and bulk FinFETs. SRAM cells are also reported to work, scaling similarly with the supply voltage (VDD) for the two FinFET integration schemes.