A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET

A 112Gb/s PAM4 wireline receiver testchip is implemented in 16nm FinFET. The receiver consists of continuous-time linear equalizers, a peaking capacitance buffer, and a 56GSa/s 64-way time-interleaved SAR ADC. The receiver achieves 2e-5 BER over a 20dB loss channel at 28GHz Nyquist while consuming 590mW power, excluding DSP.