Role of IC substrate and ESD protections in noise propagation: Design and modelling of dedicated test chip in 40 nm technology

This paper presents the design of a silicon test chip specially conceived to study the noise propagation trough the silicon substrate in order to build up a model to be used in simulating EMC performances —both emission (EME) and immunity (EMI)— and to be able to predict early in advance, before silicon fabrication, EME-EMI characteristics. The chip is realized in 40 nm CMOS technology, the one used for the realization of automotive microcontroller. Four versions of the chip are presented and some measurements are shown. This first paper focuses on emissions aspects, even if the schematic architecture and layout has been developed to cover immunity phenomenon too. To understand the role played by the silicon substrate as propagation medium (noise internally generated to outside or to convey the external environment interferences into the silicon circuitries), the ESD pin protections have been removed on two versions of the test chip. The same electrical architecture is also proposed in different layout designs: with and without the Deep N-Well (DNW) implant allowing isolation of p-well substrates, to evaluate the benefit of this process technique. Previous work is discussed, and new hypotheses and emission measurements are shown. This work is focused on the basic version of the test chip, without DNW and ESD protection, to highlight noise propagation due to the substrate only, without intervention of different physical structures.