Localized Layout Effect Related Reliability Approach in 8nm FinFETs Technology: From Transistor to Circuit.

Localized layout effect (LLE) has become a significant concern for device area, performance and reliability co-optimization due to more compact layout footprint in advanced technology, which brings about complex strain effect in the channel. In this work, the LLE related reliability has been reported on 8nm FinFETs technology for the first time demonstrating BTI degradation is sensitive to LLE, but HCI isn't. Further studies on ring oscillator (RO) provide insights for area, performance and reliability co-optimization.