Residual stresses at cavity corners in silicon-on-insulator bonded wafers

Uncontrolled residual stresses in both integrated circuit and micro-electro-mechanical system applications may affect device performance and reliability, making microscale experimental analysis of the residual stresses an essential part of process and quality control. This work studies the residual stresses generated from different processing parameters common in the manufacture of silicon-on-insulator wafers with buried cavities (cavity-SOI). The buried cavities can concentrate the residual stresses and generate localized mechanical failures. Infrared photoelasticity and optical profilometry are used here to analyze the stress state in wafers after each of several critical processing steps, each with different process parameters. It is found that the residual stresses associated with cavities in the bonded wafers may significantly increase depending upon the oxidation/etching steps and that the stress magnitude is dependent upon the particular etched cavity geometry. Process-dependent stress states and their generation mechanisms are explained for each processing step. The oxide layer grown on cavity sidewalls is found to significantly impact the residual stress at the cavity corners, with a strong dependence on buried oxide layer thickness. By selecting appropriate processing steps and parameters, the magnitude and orientation of the residual stress in the cavity-SOI wafers can be controlled to enhance reliability.